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km48c514d, KM48V514D cmos dram this is a family of 524,288 x 8 bit extended data out mode cmos drams. extended data out mode offers high speed random access of memory cells within the same row. power supply voltage(+5.0v or +3.3v), access time(-5,-6,-7), power consumption(normal or low power) and package type(soj or tsop-ii) are optional features of this family. all of this family have cas -before- ras refresh, ras -only refresh and hidden refresh capabilities. furthermore, self-refresh operation is available in l-version. this 512kx8 edo mode dra m family is fabricated using samsung s advanced cmos process to realize high band-width, low power consumption and high reliability. it may be used as main memory unit for microcomputer, personal computer and portable machines. ? part identification - km48c514d/dl (5v, 1k ref.) - KM48V514D/dl (3.3v, 1k ref.) ? extended data out mode operation ? byte read/write operation ? cas -before- ras refresh capability ? ras -only and hidden refresh capability ? self-refresh capability (l-ver only) ? ttl(5v)/lvttl(3.3v) compatible inputs and outputs ? early write or output enable controlled write ? jedec standard pinout ? available in 28-pin soj 400mil & tsop(ii) 400mil packages ? dual +5v 10% power supply(5v product) ? dual +3.3v 0.3v power supply(3.3v product) control clocks vbb generator refresh timer refresh control refresh counter row address buffer col. address buffer row decoder column decoder ras cas w vcc vss dq0 to dq7 a0 - a9 a0 - a8 memory array 524,288 x8 cells samsung electronics co., ltd. reserves the right to change products and specifications without notice. 512k x 8bit cmos dynamic ram with extended data out description features functional block diagram ? refresh cycles part no. v cc refresh cycle refresh period normal l-ver c514d 5v 1k 16ms 128ms v514d 3.3v ? performance range speed t rac t cac t rc t hpc remark -5 50ns 15ns 84ns 20ns 5v only -6 60ns 15ns 104ns 25ns 5v/3.3v -7 70ns 20ns 124ns 30ns 5v/3.3v ? active power dissipation speed 3.3v (1k ref.) 5v (1k ref.) -5 - 470 -6 255 385 -7 235 360 unit : mw s e n s e a m p s & i / o data out buffer data in buffer oe .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pin configuration (top views) pin name pin function a0 - a9 address inputs dq0 - 7 data in/out v ss ground ras row address strobe cas column address strobe w read/write input oe data output enable v cc power(+5v) power(+3.3v) n.c no connection v cc dq0 dq1 dq2 dq3 n.c w ras a9 a0 a1 a2 a3 v cc v ss dq7 dq6 dq5 dq4 cas oe n.c a8 a7 a6 a5 a4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (soj) (tsop-ii) v cc dq0 dq1 dq2 dq3 n.c w ras a9 a0 a1 a2 a3 v cc v ss dq7 dq6 dq5 dq4 cas oe n.c a8 a7 a6 a5 a4 v ss ? km48c/v514dj ? km48c/v514dt .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram absolute maximum ratings * permanent device damage may occur if "absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol rating units 3.3v 5v voltage on any pin relative to v ss v in, v out -0.5 to +4.6 -1.0 to +7.0 v voltage on v cc supply relative to v ss v cc -0.5 to +4.6 -1.0 to +7.0 v storage temperature tstg -55 to +150 -55 to +150 c power dissipation p d 1 1 w short circuit output current i os 50 50 ma recommended operating conditions (voltage referenced to vss, t a = 0 to 70 c) *1 : v cc +1.3v/15ns(3.3v), v cc +2.0/20ns(5v), pulse width is measured at v cc *2 : -1.3v/15ns(3.3v), -2.0v/20ns(5v), pulse width is measured at v ss parameter symbol 3.3v 5v units min typ max min typ max supply voltage v cc 3.0 3.3 3.6 4.5 5.0 5.5 v ground v ss 0 0 0 0 0 0 v input high voltage v ih 2.0 - v cc +0.3 *1 2.4 - v cc +1.0 *1 v input low voltage v il -0.3 *2 - 0.8 -1.0 *2 - 0.8 v dc and operating characteristics (recommended operating conditions unless otherwise noted.) parameter symbol min max units 3.3v input leakage current (any input 0 v in v in +0.3v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-2ma) v oh 2.4 - v output low voltage level(i ol =2ma) v ol - 0.4 v 5v input leakage current (any input 0 v in v in +0.5v, all other input pins not under test=0 volt) i i(l) -5 5 ua output leakage current (data out is disabled, 0v v out v cc ) i o(l) -5 5 ua output high voltage level(i oh =-5ma) v oh 2.4 - v output low voltage level(i ol =4.2ma) v ol - 0.4 v .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram *note : i cc1 , i cc3 , i cc4 and i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 , i cc3 , i cc6 and i cc7, address can be changed maximum once while ras =v il . in i cc4 , address can be changed maximum once within one hyper page mode cycle time, t hpc . dc and operating characteristics i cc1 * : operating current ( ras and cas , address cycling @ t rc =min.) i cc2 : standby current ( ras = cas = w =v ih ) i cc3 * : ras -only refresh current ( cas =v ih , ras , address cycling @ t rc =min.) i cc4 * : hyper page mode current ( ras =v il , cas , address cycling @ t hpc =min.) i cc5 : standby current ( ras = cas = w =v cc -0.2v) i cc6 * : cas -before- ras refresh current ( ras and cas cycling @ t rc =min.) i cc7 : battery back-up current, average power supply current, battery back-up mode input high voltage(v ih )=v cc -0.2v, input low voltage(v il )=0.2v, cas =0.2v, dq=don t care, t rc =125us, t ras =t ras min~300ns i ccs : self refresh current ras = cas =v il , w = oe =a0 ~ a9=v cc -0.2v or 0.2v dq0 ~ dq7=v cc -0.2v, 0.2v or open symbol power speed max units KM48V514D km48c514d i cc1 don t care -5 -6 -7 - 70 65 85 70 65 ma ma ma i cc2 don t care don t care 1 2 ma i cc3 don' -5 -6 -7 - 70 65 85 70 65 ma ma ma i cc4 don t care -5 -6 -7 - 55 50 85 70 65 ma ma ma i cc5 normal l don t care 0.5 100 1 150 ma ua i cc6 don t care -5 -6 -7 - 70 65 85 70 65 ma ma ma i cc7 l don t care 200 300 ua i ccs l don t care 100 200 ua (recommended operating conditions unless otherwise noted.) .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram capacitance (t a =25 c, v cc =5v or 3.3v, f=1mhz) parameter symbol min max units input capacitance [a0 ~ a9] c in1 - 5 pf input capacitance [ ras , cas , w , oe ] c in2 - 7 pf output capacitance [dq0 - dq7] c dq - 7 pf test condition (5v device) : v cc =5.0v 10%, vih/vil=2.4/0.8v, voh/vol=2.0/0.8v note) *1 : 5v only parameter symbol -5 *1 -6 -7 units notes min max min max min max random read or write cycle time t rc 84 104 124 ns read-modify-write cycle time t rwc 116 138 163 ns access time from ras t rac 50 60 70 ns 3,4,10 access time from cas t cac 15 15 20 ns 3,4,5 access time from column address t aa 25 30 35 ns 3,10 cas to output in low-z t clz 3 3 3 ns 3 output buffer turn-off delay from cas t cez 3 13 3 13 3 18 ns 6,12 transition time (rise and fall) t t 2 50 2 50 2 50 ns 2 ras precharge time t rp 30 40 50 ns ras pulse width t ras 50 10k 60 10k 70 10k ns ras hold time t rsh 17 17 20 ns cas hold time t csh 40 50 60 ns cas pulse width t cas 8 10k 10 10k 15 10k ns ras to cas delay time t rcd 20 35 20 45 20 50 ns 4 ras to column address delay time t rad 15 25 15 30 15 35 ns 10 cas to ras precharge time t crp 5 5 5 ns row address set-up time t asr 0 0 0 ns row address hold time t rah 10 10 10 ns column address set-up time t asc 0 0 0 ns column address hold time t cah 8 10 15 ns column address to ras lead time t ral 25 30 35 ns read command set-up time t rcs 0 0 0 ns read command hold time referenced to cas t rch 0 0 0 ns 8 read command hold time referenced to ras t rrh 0 0 0 ns 8 write command set-up time t wcs 0 0 0 ns 7 write command hold time t wch 10 10 10 ns write command pulse width t wp 10 10 10 ns write command to ras lead time t rwl 13 15 15 ns write command to cas lead time t cwl 8 10 15 ns ac characteristics (0 c t a 70 c, see note 1,2) test condition (3.3v device) : v cc =3.3v 0.3v, vih/vil=2.2/0.7v, voh/vol=2.0/0.8v .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram ac characteristics (continued) note) *1 : 5v only parameter symbol -5 *1 -6 -7 units notes min max min max min max data set-up time t ds 0 0 0 ns 9 data hold time t dh 8 10 15 ns 9 refresh period (normal) t ref 16 16 16 ms refresh period (l-ver) t ref 128 128 128 ms cas to w delay time t cwd 32 32 42 ns 7 ras to w delay time t rwd 67 77 92 ns 7 column address to w delay time t awd 42 47 57 ns 7 cas precharge to w delay time t cpwd 45 52 62 ns 7 cas set-up time ( cas -before- ras refresh) t csr 5 5 5 ns cas hold time ( cas -before- ras refresh) t chr 10 10 10 ns ras to cas precharge time t rpc 5 5 5 ns cas precharge time ( c -b- r counter test cycle) t cpt 20 20 25 ns access time from cas precharge t cpa 28 35 40 ns 3 hyper page mode cycle time t hpc 20 25 30 ns 11 hyper page read-modify-write cycle time t hprwc 47 56 71 ns 11 cas precharge time (hyper page cycle) t cp 8 10 10 ns ras pulse width (hyper page cycle) t rasp 50 100k 60 100k 70 100k ns ras hold time from cas precharge t rhcp 30 35 40 ns oe access time t oea 15 15 20 ns 3 oe to data delay t oed 13 13 18 ns output buffer turn off delay time from oe t oez 3 13 3 13 3 18 ns 6 oe to output in low-z t olz 3 3 3 ns oe command hold time t oeh 15 15 20 ns output data hold time t doh 5 5 5 ns output buffer turn off delay from ras t rez 3 15 3 15 3 20 ns 6,12 output buffer turn off delay from w t wez 3 13 3 13 3 18 ns 6 w to data delay t wed 13 13 18 ns oe to cas hold time t och 5 5 5 ns cas hold time to oe t cho 5 5 5 ns oe precharge time t oep 5 5 5 ns w pulse width (hyper page cycle) t wpe 5 5 5 ns ras pulse width ( c -b- r self refresh) t rass 100 100 100 us 13,14,15 ras precharge time ( c -b- r self refresh) t rps 90 110 130 ns 13,14,15 cas hold time ( c -b- r self refresh) t chs -50 -50 -50 ns 13,14,15 .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram an initial pause of 200us is required after power-up followed by any 8 ras -only refresh or cas -before- ras refresh cycles before proper device operation is achieved. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih (min) and v il (max) and are assumed to be 2ns for all inputs. measured with a load equivalent to 2 ttl(5v)/1 ttl(3.3v) loads and 100pf. operation within the t rcd (max) limit insures that t rac (max) can be met. t rcd (max) is specified as a reference point only. if t rcd is greater than the specified t rcd (max) limit, then access time is controlled exclusively by t cac . assumes that t rcd 3 t rcd (max). this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh or v ol . t wcs , t rwd , t cwd , t awd and t cpwd are non restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs 3 t wcs (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. if t cwd 3 t cwd (min), t rwd 3 t rwd (min), t awd 3 t awd (min) and t cpwd 3 t cpwd (min) then the cycle is a read-modify-write cycle and the data output will contain the data read from the selected address. if neither of the above con- ditions is satisfied, the condition of the data out is indeterminate. either t rch or t rrh must be satisfied for a read cycle. these parameters are referenced to cas falling edge in early write cycles and to w falling edge in oe controlled write cycle and read-modify-write cycles. operation within the t rad (max) limit insures that t rac (max) can be met. t rad (max) is specified as a reference point only. if t rad is greater than the specified t rad (max) limit, then access time is controlled by t aa . t asc 3 6ns, assume t t = 2.0ns if ras goes high before cas high going, the open circuit condition of the output is achieved by cas high going. if cas goes high before ras high going, the open circuit condition of the output is achieved by ras high going. if t rass 3 100us, then ras precharge time must use t rps instead of t rp . for ras -only refresh and burst cas -before- ras refresh mode, 1024(1k) cycle of burst refresh must be executed within 16ms before and after self refresh, in order to meet refresh specification. for distributed cas -before- ras with 15.6us interval, cas -before- ras refresh should be executed with in 15.6us immedi- ately before and after self refresh in order to meet refresh specification. 7. 6. 5. 10. 9. 8. 12. 11. 3. 2. 1. 4. 13. 14. 15. notes .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v oh - v ol - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t asr t rah t asc t cah t crp t aa t oea t clz t rac open t rch don t care undefined t rad t rrh data-out t rez t rcs read cycle t oez t cez t wez dq0 ~ dq3(7) t olz t cac .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram t wcs note : d out = open write cycle ( early write ) ras v ih - v il - v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp don t care undefined t wch t wp cas t rwl t cwl t ds t dh data-in dq0 ~ dq3(7) .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram note : d out = open write cycle ( oe controlled write ) ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v ih - v il - dq0 ~ dq3(7) column address row address t ras t rc t crp t rp t csh t rsh t rcd t cas t ral t rad t asr t rah t asc t cah t crp t wp don t care undefined cas v ih - v il - t rwl t cwl t dh t oeh t oed data-in t ds .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram read - modify - write cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - dq0 ~ dq3(7) row addr t ras t rwc t rp t rsh t rcd t cas t csh t rad t asr t rah t asc t cah t crp valid t wp don t care t rwl t cwl t oez t oea t oed t awd t cwd t rwd data-out undefined valid data-in t rac t aa t cac t clz t ds t dh column address t olz .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram t doh hyper page read cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp t rcd t asr t crp don t care undefined v oh - v ol - dq0 ~ dq3(7) t oep column address t cas t cas t cas t cas t cp t cp t cp t hpc t hpc t hpc t rhcp t csh t rad t rah t asc t cah t cah t cah t asc t cah t rcs t aa t rch t asc column address column addr valid data-out t oez t oea t oep t aa t cac t aa t cpa t cpa valid data-out valid data-out t oez t clz t rac t oea t olz t cac t rrh t cho t rez t oez t cac t och t cpa t cac valid data-out ? t asc t aa t ral t oea .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr. t rasp t rp t rcd t asr t crp don t care hyper page write cycle ( early write ) undefined v ih - v il - dq0 ~ dq3(7) t rhcp t rad t rah t cah t cah t asc t cah t asc valid data-in t ds ? column address column address t cas t cp t cas t cp t cas t rsh ? t csh t asc ? ? t wp t wcs t wch t wp t wcs t wch t wp t wch ? ? ? valid data-in valid data-in ? ? t dh t ds t dh t ds t dh t cwl t cwl t cwl t rwl note : d out = open t hpc t hpc t wcs t ral .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram don t care hyper page read-modify-write cycle undefined ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - v i/oh - v i/ol - row addr t csh t rasp t rp t asr t rcd t cp t rad t cah t wp t dh col. addr col. addr t cas t cas t crp t asc t cah t ral t rcs t cwl t cwd t awd t rwd t wp t cwd t awd t cwl t rac t oea t clz t oez t cpwd t oed t asc t clz t oea t cac t aa t dh t oed t rwl t crp t ds t oez valid data-out valid data-in valid data-out valid data-in t ds dq0 ~ dq3(7) t rsh t olz t olz t hprwc t cac t aa t rah .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram hyper page read and write mixed cycle ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - column address row addr t rasp t rp don t care undefined v i/oh - v i/ol - dq0 ~ dq3(7) t wez t cp t cp t hpc t hpc t hpc t rad t rah t asc t cah t cah t cah t asc t cah t rch t rcs t rcs t rch t asc column address col. addr valid data-out t rez t aa t wcs valid data-out valid data-out valid data-in t rac col. addr t cas t asr t cas t cas t cas t asc t cp t rch t wch t wpe t clz t cpa t wed t aa t wez t ds t dh t cac t oea read( t cac ) read( t cpa ) write read( t aa ) t rhcp t ral t clz .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram don t care ras - only refresh cycle* note : w , oe , d in = don t care undefined d out = open ras v ih - v il - cas v ih - v il - a v ih - v il - row addr t rc t rp t asr t crp t ras t rah t rpc t crp open cas - before - ras refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rc t rp t ras t rpc t cp t rpc t csr t chr t cez v oh - v ol - dq0 ~ dq3(7) t wrp t wrh w v ih - v il - t rp .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram hidden refresh cycle ( read ) t oez data-out t rp ras v ih - v il - cas v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t chr t rcd t rsh t rad t asr t rah t asc t crp don t care undefined v oh - v ol - dq0 ~ dq3(7) t wrh column address t oea t ras t rc t cah t rcs t aa t rac t clz t cac t cez open t rp t wez t rez t olz t ral .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram t crp t wcs t rp ras v ih - v il - a v ih - v il - w v ih - v il - oe v ih - v il - row address t ras t rc t rad t asr t rah t asc don t care hidden refresh cycle ( write ) undefined cas v ih - v il - v ih - v il - dq0 ~ dq3(7) t rsh t rcd t wrh column address t ras t rc t chr t cah t wrp t ds note : d out = open t wp t wch data-in t dh t rp t ral .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram cas -before- ras refresh counter test cycle ras v ih - v il - cas v ih - v il - a v ih - v il - column address t ras t rsh t chr t ral t csr t cpt t rp t cas t asc t cah read cycle v oh - v ol - dq0 ~ dq3(7) t rez t clz write cycle v ih - v il - data-in dq0 ~ dq3(7) t dh t ds w v ih - v il - t wp t cwd t cwl t rwl read-modify-write t awd v ih - v il - oe t oea t aa t cac t ds t dh valid data-out v i/oh - v i/ol - dq0 ~ dq3(7) don t care undefined v ih - v il - oe t oea t oez oe v ih - v il - t rcs t clz t oez t oed t wrp t wrh t rrh t rch t rcs t cac t aa v ih - v il - w t wrp t wrh t wcs t wch t cwl v ih - v il - w t wp t rwl t wrp t wrh valid data-in t wez t cez data-out .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram open cas - before - ras self refresh cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rps t rass t rpc t cp t rpc t csr t cez v oh - v ol - dq0 ~ dq3(7) t rp don t care undefined t chs t wrp t wrh w v ih - v il - open test mode in cycle note : oe , a = don t care ras v ih - v il - cas v ih - v il - t rp t rc t rpc t cp t rpc t csr t off v oh - v ol - dq0 ~ dq3(7) t wts t wth w v ih - v il - t chr t rp t ras .com .com .com .com .com 4 .com u datasheet
km48c514d, KM48V514D cmos dram 28 soj 400mil 0 . 4 0 0 ( 1 0 . 1 6 ) 0 . 4 3 5 ( 1 1 . 0 6 ) 0 . 4 4 5 ( 1 1 . 3 0 ) 0.730 (18.54) 0.720 (18.30) max 0.741 (18.82) m a x 0 . 1 4 8 ( 3 . 7 6 ) 0.0375 (0.95) 0.050 (1.27) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 . 3 6 0 ( 9 . 1 5 ) 0 . 3 8 0 ( 9 . 6 5 ) min #28 units : inches (millimeters) package dimension 28 tsop(ii) 400mil max 0.047 (1.20) min 0.002 (0.05) 0.020 (0.50) 0.012 (0.30) 0.050 (1.27) 0.037 (0.95) 0.721 (18.31) 0.729 (18.51) 0.741 (18.81) max 0.010 (0.25) 0.004 (0.10) 0 . 4 0 0 ( 1 0 . 1 6 ) 0 . 4 7 1 ( 1 1 . 9 6 ) 0 . 4 5 5 ( 1 1 . 5 6 ) units : inches (millimeters) 0~8 0.030 (0.75) 0.018 (0.45) typ 0.010 (0.25) o .com .com .com .com 4 .com u datasheet

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